Particular embodiments generally relate to a universal asynchronous receiver/transmitter (UART).
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A UART may be used for serial communications. A UART transmitter may take bytes of data in a parallel form and transmit individual bits sequentially. A UART receiver reassembles the bits into complete bytes. The UART receiver synchronizes itself at the start of every frame (e.g., a byte of data) to maintain reliable data sampling. FIG. 1 shows a conventional data frame 100. Data frame 100 may include a start bit 102, eight data bits 104, and a stop bit 106. The bits in data frame 100 are sent serially from the UART transmitter to the UART receiver.
The UART receiver uses a UART reference clock to sample the serial data stream that is received. The UART reference clock is typically at a higher frequency, such as 16 times, than a baud rate of the serial data stream.
FIG. 2 shows sampling of the serial data stream. A UART reference clock 202 is provided along with a serial data stream 204. A start bit 102 is recognized at a falling edge shown at 206.
The UART receiver may then reset its counters on this falling edge. The UART receiver counts a number of clock cycles of reference clock 202 such that the serial data stream's bits are sampled mid-bit. For example, if there are 16 clock cycles during the transfer of a bit, then after 8 clock cycles, the start bit may be sampled at 208. The start bit is sampled mid-bit to check that the level is still low to ensure that the detected falling edge was a start bit and not noise. Then, 16 clock cycles thereafter, a first bit D0 is sampled mid-bit. This process continues as each bit is sampled every 16 clock cycles until a stop bit (not shown) is received.
Problems may occur with the UART timing, which may cause data corruption. FIG. 3 shows an example of a receiving range for the serial data stream. It is preferable to sample the data bit at the mid-point because there may be bit transition times. For example, bit transition times are shown at an area 302 where the serial data stream is changing states. It is not desirable to sample the serial data stream in area 302. A data eye 304 is a portion where it is desirable to sample the data bit. As shown, a first limit and a second limit show the limits of sampling in which a correct reading may be determined and also an optimum point 306, which is the mid-point.
For a “nasty” scenario, which only allows sampling within the middle 50% of the bit time, an error budget may be small. For example, the error budget may be +/− four samples for a 16× reference clock or only +/− two samples for 8× reference clock. Thus, to allow larger error budgets, the UART reference clock is designed to be a larger multiple of the desired baud rate. For example, a faster reference clock allows a finer resolution of a time to sample the serial data stream. However, to have the faster UART reference clock, a numerical computation oscillator (NCO) or a fraction divider may be needed to have an accurate reference clock to support the throughput of the baud rate. The NCO circuitry may be very complicated, costly, and include an expensive external crystal or internal phase lock loop (PLL). Additionally, using the higher frequency UART reference clocks consume more power and increase die size.